View ISL614407_706508.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
ISL6144
Data Sheet February 15, 2007 FN9131.3
High Voltage ORing MOSFET Controller
The ISL6144 ORing MOSFET Controller and a suitably sized N-Channel power MOSFET(s) increases power distribution efficiency and availability when replacing a power ORing diode in high current applications. In a multiple supply, fault tolerant, redundant power distribution system, paralleled similar power supplies contribute equally to the load current through various power sharing schemes. Regardless of the scheme, a common design practice is to include discrete ORing power diodes to protect against reverse current flow should one of the power supplies develop a catastrophic output short to ground. In addition, reverse current can occur if the current sharing scheme fails and an individual power supply voltage falls significantly below the others. Although the discrete ORing diode solution has been used for some time and is inexpensive to implement, it has some drawbacks. The primary downside is the increased power dissipation loss in the ORing diodes as power requirements for systems increase. Another disadvantage when using an ORing diode would be failure to detect a shorted or open ORing diode, jeopardizing power system reliability. An open diode reduces the system to single point of failure while a diode short might pose a hazard to technical personnel servicing the system while unaware of this failure. The ISL6144 can be used in 10V to 75V systems having similar power sources and has an internal charge pump to provide a floating gate drive for the N-Channel ORing MOSFET. The High Speed (HS) Comparator protects the common bus from individual power supply shorts by turning off the shorted feed's ORing MOSFET in less than 300ns and ensuring low reverse current. An external resistor-programmable detection level for the HS Comparator allows users to set the N-Channel MOSFET "VOUT - VIN" trip point to adjust control sensitivity to power supply noise. The Hysteretic Regulating (HR) Amplifier provides a slow turnoff of the ORing MOSFET. This turn-off is achieved in less than 100s when one of the sourcing power supplies is shutdown slowly for system diagnostics, ensuring zero reverse current. This slow turn-off mechanism also reacts to output voltage droop, degradation, or power-down. An open drain FAULT pin will indicate that a fault has occurred. The fault detection circuitry covers different types of failures; including dead short in the sourcing supply, a short of any two ORing MOSFET terminals, or a blown fuse in the power distribution path.
Features
* Wide Supply Voltage Range +10V to +75V * Transient Rating to +100V * Reverse Current Fault Isolation * Internal Charge Pump Allows the use of N-Channel MOSFET * HS Comparator Provides Very Fast <0.3s Response Time to Dead Shorts on Sourcing Supply. HS Comparator also has Resistor-adjustable Trip Level * HR Amplifier allows Quiet, <100s MOSFET Turn-off for Power Supply Slow Shut Down * Open Drain, Active Low Fault Output with 120s Delay * Provided in Packages Compliant to UL60950 (UL1950) Creepage Requirements * QFN Package: - Compliant to JEDEC PUB95 MO-220 QFN - Quad Flat No Leads - Package Outline - Near Chip Scale Package footprint, which improves PCB efficiency and has a thinner profile * Pb-Free Plus Anneal Available (RoHS Compliant)
Applications
* ORing MOSFET Control in Power Distribution Systems * N + 1 Redundant Distributed Power Systems * File and Network Servers (12V and 48V) * Telecom/Datacom Systems
Ordering Information
PART NUMBER ISL6144IV* PART MARKING ISL61 44IV TEMP. RANGE (C) -40 to +105 -40 to +105 PKG. DWG. #
PACKAGE
16 Ld TSSOP M16.173 16 Ld TSSOP M16.173 (Pb-Free) 20 Ld 5x5 QFN L20.5x5 20 Ld 5x5 QFN L20.5x5 (Pb-Free)
ISL6144IVZA* ISL61 44IVZ (See Note) ISL6144IR* ISL 6144IR
-40 to +105 -40 to +105
ISL6144IRZA* ISL6144 IRZ (See Note)
NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. *Add "-T" suffix for tape and reel.
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2004, 2006-2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
ISL6144 Pinouts
ISL6144 (16 LD TSSOP) TOP VIEW ISL6144 (20 LD 5x5 QFN) TOP VIEW
GATE NC NC NC 17 NC 16 15 VOUT 14 COMP 13 VSET 12 NC 11 NC 6 NC 7 GND 8 NC 9 FAULT 10 NC
GATE VIN HVREF NC NC NC NC GND
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
VOUT COMP VSET NC NC NC NC FAULT VIN HVREF NC NC NC 1 2 3 4 5
20
19
18
Pin Descriptions
TSSOP PIN # 1 2 3 8 9 QFN PIN # 19 1 2 7 9 SYMBOL GATE FUNCTION External FET Gate Drive Power Supply Connection Chip High Voltage Reference Chip Ground Reference Fault Output DESCRIPTION Allows active control of external N-Channel FET gate to perform ORing function. Chip bias input. Also provides a sensing node for external FET control. Low side of floating high voltage reference for all of the HV chip circuitry. Chip ground reference point. Provides an open drain active low output as an indication that a fault has occurred: GATE is OFF (GATE < VIN + 0.37V) or other types of faults resulting in VIN - VOUT > 0.41V.
VIN
HVREF GND FAULT
14 15 16 4-7, 10-13
13 14 15 3-6, 8, 10-12, 16-18, 20
VSET COMP VOUT NC
Low Side Connection for Trip Level Resistor connected to COMP provides adjustable "Vd-Vs" trip level along with pin COMP. High Side Connection for HS Comparator Trip Level Chip Bias and Load Connection No Connection Resistor connected to VOUT provides sense point for the adjustable Vd-Vs trip level along with pin VSET. Provides the second sensing node for external FET control and chip output bias.
2
FN9131.3 February 15, 2007
ISL6144 General Application Circuit
+
-
AC/DC 1 VIN 5V GATE VOUT ISL6144 COMP
DC/DC 1 GATE VOUT ISL6144 HVREF COMP VIN 5V FAULT GND VSET LOAD "+12V"
HVREF
FAULT VSET GND
AC POWER
+48VDC BUS
AC/DC N+1 GATE VOUT ISL6144 COMP HVREF VIN 5V FAULT VSET GND
DC/DC N+1 GATE VOUT ISL6144 COMP HVREF VIN 5V FAULT VSET GND
NOTES: 5. AC/DC 1 through (N + 1) are multistage AC/DC converters which include AC/DC rectification stage and a DC/DC Converter with a +48VDC output (also might include a Power Factor Correction stage). 6. DC/DC Converter 1 through (N + 1) are DC/DC converters to provide additional Intermediate Bus 7. Load "+12V" and Load "+48V" might include other DC/DC converter stages to provide lower voltages such as 15V, 5V, +3.3V, +2.5V, +1.8V etc. 8. Fuse location might vary depending on power system architecture.
FIGURE 1. ISL6144 GENERAL APPLICATION CIRCUIT IN A DISTRIBUTED POWER SYSTEM
3
+12VDC BUS
FN9131.3 February 15, 2007
LOAD "+48V"
ISL6144 Simplified Block Diagram
SOURCE 2 10V TO 75V D2 * F2**
C1
VIN GATE VOUT HVREF COMP ISL6144 FAULT GND VSET
R 1 C2 R2 * D1, D2 PARASITIC DIODES **F1, F2 FUSES COULD ALSO BE PLACED ON THE INPUT SIDE BEFORE THE VIN PIN. THIS PLACEMENT DEPENDS ON POWER SYSTEM ARCHITECTURE.
D1*
F1** SOURCE 1 10V TO 75V
VIN
GATE LOAD
VOUT GATE LOGIC AND CHARGE PUMP C1 FAULT DETECTION 5.5V 20mV LEVEL SHIFT + REG AMPLIFIER 2A* HVREF 5mA HS COMP + VSET R2 -+ HIGH VOLTAGE PASS AND CLAMPING R1 5.3V 0.1mA
C2
COMP
DELAY 100s FAULT UV COMP + 0.6V
BIAS AND REF
0.2 mA 1.5mA 1.5mA
GND
4
FN9131.3 February 15, 2007
ISL6144
Absolute Maximum Ratings TA = +25C
VIN, VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +100V
GATE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN +12V HVREF. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VIN -5V COMP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT VSET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to VOUT -5V FAULT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to 16V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA (C/W) JC (C/W) TSSOP Package (Note 1) . . . . . . . . . . 90 N/A QFN Package (Notes 3, 4). . . . . . . . . . 35 5 Maximum Junction Temperature (Plastic Package) . . . . . . . +150C Maximum Storage Temperature Range . . . . . . . . . .-65C to +150C Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . +300C
Operating Conditions
Supply Voltage Range . . . . . . . . . . . . . . . . . . . . . . . . . +10 to +75V Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . -40C to +105C
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. +150C max junction temperature is intended for short periods of time to prevent shortening the lifetime. Operation close to +150C junction may trigger the shutdown of the device even before +150C, since this number is specified as typical.
NOTES: 1. JA is measured with the component mounted on a high effective thermal conductivity test board in free air. (See Tech Brief, #TB379.1 for details.) 2. All voltages are relative to GND, unless otherwise specified. 3. For JC, the "case temp" location is the center of the exposed metal pad on the package underside. 4. JA is measured in free air with the component mounted on a high effective thermal conductivity test board with "die attach" features. (See Tech Brief, #TB379 for details.)
Electrical Specifications
PARAMETER BIAS "VIN" POR Rising 12V Bias Current 48V Bias Current 75V Bias Current GATE Charge Pump Voltage Gate Low Voltage Level Low Pull Down Current High Pull Down Current Slow Turn-off Time Fast Turn-off Time Start-up "Turn-On" Time GATE Turn-On Current
VIN = 48V, TA = -40C to +105C, Unless Otherwise Specified SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
PORL2H I12V I48V I75V
VIN Rising to VGATE > VIN + 7.5V VIN = 12V, VGATE = VIN + VGQP VIN = 48V, VGATE = VIN + VGQP VIN = 75V, VGATE = VIN + VGQP
10 -
3.5 4.5 5
-
V mA mA mA
VGQP VGL IPDL (Note 5) IPDH (Note 5) ttoffs ttoff tON ION (Note 5)
VIN = 12V to 75V VIN - VOUT < 0V Cgs = 39nF, IPDL = Cgs * dVgs/Ttofs Cgs = 39nF, IPDH = Cgs * dVgs/Ttoff Cgs = 39nF Turn-off from VGATE = VIN + VGQP to VIN + 1V with Cgs = 39nF (includes HS Comparator delay time) Turn-on from VGATE = VIN to VIN + 7.5V into 39nF VIN = 10V to 75V
VIN + 9 -0.3 -
VIN + 10.5 VIN + 12 VIN 5 2 250 1 1 VIN + 0.5 100 300 -
V V mA A s ns ms mA
CONTROL AND REGULATION I/O HR Amplifier Forward Voltage Regulation HS COMP Externally Programmable Threshold HS Comparator Offset Voltage VFWD_HR ISL6144 controls voltage across FET Vds to VFWD_HR during static forward operation at loads resulting in I * rDS(ON) < VFWD_HR Externally programmable threshold for noise sensitivity (system dependent), typical 0.05 to 0.3V 10 20 30 mV
VTH(HS) (Note 5) VOS(HS)
0 -40
0.05 0
5.3 25
V mV
5
FN9131.3 February 15, 2007
ISL6144
Electrical Specifications
PARAMETER COMP Input Current (bias current) HVREF Voltage (VIN - HVREF) VSET Voltage (VOUT - VSET) Fault Low Output Voltage Fault Sink Current Fault Leakage Current Fault Delay - Low to High NOTES: 5. The denotes parameters which are guaranteed by design and not production tested. 6. Specifications to +105C and -40C are guaranteed by design and not production tested. VIN = 48V, TA = -40C to +105C, Unless Otherwise Specified (Continued) SYMBOL ICOMP HVREF(VZ) VIN = 10V to 75V TEST CONDITIONS MIN 4 TYP 1.1 5.5 5.3 120 MAX 0.5 10 UNITS A V V V mA A s
VREF(VSET) VIN = 10V to 75V VFLT_L IFLT_SINK IFLT_LEAK TFLT VIN - VOUT < 0V, VGATE = VGL FAULT = VFLT_L, VIN < VOUT, VGATE = VGL FAULT = "VFLT_H", VIN > VOUT, VGATE = VIN + VGQP GATE = VGL to FAULT = VFLT_L
Functional Pin Description
GATE
This is the Gate Drive output of the external N-Channel MOSFET generated by the IC internal charge pump. Gate turn-on time is typically 1ms.
FAULT
Open-Drain pull-down FAULT Output with internal on chip filtering (TFLT). The ISL6144 fault detection circuitry will pull down this pin to GND as soon as it detects a fault. Different types of faults and their detection mechanisms are discussed in more detail in the Block Diagram Description section.
VIN
Input bias pin connected to the sourcing supply side (ORing MOSFET Source). Also serves as the sense pin to determine the sourcing supply voltage. The ORing MOSFET will be turned off when VIN becomes lower than VOUT by a value more than the externally set threshold.
GND
IC ground reference.
Detailed Description
The ISL6144 and a suitably sized N-Channel power MOSFET(s) increases power distribution efficiency and availability when replacing a power ORing diode in high current applications. Refer to the Application Consideration section for power saving when using ISL6144 with an N-channel ORing MOSFET compared to a typical ORing diode.
VOUT
Connected to the Load side (ORing MOSFET Drain). This is the VOUT sense pin connected to the load. This is the common connection point for multiple paralleled supplies. VOUT is compared to VIN to determine when the ORing FET has to be turned off.
Functional Block Description
Regulating Amplifier-Slow (Quiet) Turn-off
A Hysteretic Regulating (HR) Amplifier is used for a Quiet/ Slow turn-off mechanism. This slow turn-off is initiated when the sourcing power supply is turned off slowly for system diagnostics. Under normal operating conditions as VOUT pulls up to 20mV below VIN (VIN - 20mV > VOUT), the HR Amplifier regulates the gate voltage to keep the 20mV (VFWD_HR) forward voltage drop across the ORing MOSFET (Vs - Vd). This will continue until the load current exceeds the MOSFET ability to deliver the current with Vsd of 20mV. In this case, Gate will be charged to the full charge pump voltage (VGQP) to fully enhance the MOSFET. At this point, the MOSFET will be fully enhanced and behave as a constant resistor valued at the rDS(ON). Once VIN starts to drop below VOUT, regulation cannot be maintained and the output of the HR Amp is pulled high and the gate is pulled down to VIN slowly in less than a 100s. As a result, the ORing FET is turned off, avoiding reverse current as well as voltage and current stresses on supply components.
HVREF
Low side of the internal IC High Voltage Reference used by internal circuitry, also available as an external pin for additional external capacitor connection.
COMP
This is the high side connection for the HS Comparator trip level setting (VTH(HS)). Resistor R1, connected between COMP and VOUT along with resistor R2, provides adjustable VOUT - VIN trip level (0V to 5V). This provides flexibility to externally set the desired level depending on particular system requirement.
VSET
Low side connection for the HS Comparator trip level setting A second resistor R2 connected between VSET and COMP provides adjustable "VIN - VOUT" level along with R1.
6
FN9131.3 February 15, 2007
ISL6144
The slow turn-off is achieved in two stages. The first stage starts with a slow turn-off action and lasts for up to 20s. The gate pull down current for the first stage is 2mA. The second slow turn-off stage completes the gate turn-off with a 10mA pull down current. The 20s delay filters out any false trip off due to noise or glitches that might be present on the supply line. The gate turn-on and gate turn-off drivers have a 50kHz filter to reduce the variation in FET forward voltage drop (and FET gate voltage) due to normal SMPS system switching noises (typically higher than 50kHz). These filters do not affect the total turn-on or slow turn-off times. Special system design precautions must be taken to insure that no AC mains related low frequency noise will be present at the input or output of ISL6144. Filters and multiple power conversion stages, which are part of any distributed DC power system, normally filter out all such noise. The fault can be detected and isolated by using the ISL6144 and an N-Channel ORing MOSFET. VIN is compared to VCOMP, and whenever:
V IN < V COMP; where V COMP = V OUT - V TH ( HS ) VTH(HS) is defined below (EQ. 2)
The fast turn-off mechanism will be activated and the MOSFET(s) will be turned off very quickly. The speed of this turn-off depends on the amount of equivalent gate loading capacitance. For an equivalent Cgs = 39nF. The gate turn-off time is <300ns and gate pull down current is 2A. The level of VTH(HS) (HS Comparator trip level) is adjustable by means of external resistors R1 and R2 to a value theoretically ranging from 0V to 5.3V. Typical values are 0.05V to 0.3V. This is done in order to avoid false turn-off due to noise or minor glitches present in the DC switching power supply. The threshold voltage is calculated as:
R1 V TH ( HS ) = ------------------------- V REF ( VSET ) ( R1 + R2 ) (EQ. 3)
HS Comparator-Fast Turn-off
There is a High Speed (HS) Comparator used for fast turnoff of the ORing MOSFET to protect the common bus against hard short faults at a sourcing power supply output (refer to Figure 3). During normal operation the gate of the ORing MOSFET is charge pumped to a voltage that depends on whether it is in the 20mV regulation mode or fully enhanced. In this case:
V OUT = V IN - I OUT * r DS(ON ) (EQ. 1)
If a dead short fault occurs in the sourcing supply, it causes VIN to drop very quickly while VOUT is not affected as more than one supply are paralleled. In the absence of the ISL6144 functionality, a very high reverse current will flow from Output to the Input supply pulling down the common DC Bus, resulting in an overall "catastrophic" system failure.
FROM SOURCING SUPPLY TO SHARED LOAD
Where VREF(VSET) is an internal zener reference (5.3V typical) between VOUT and VSET pins. R1 and R2 must be chosen such that their sum is about 50k. An external capacitor, C2, is needed between VOUT and COMP pins to provide high frequency decoupling. The HS comparator has an internal delay time on the order of 50ns, which is part of the <300ns overall turn-off time specification (with Cgs = 39nF).
Gate Logic and Charge Pump
The IC has two charge pumps: The first charge pump generates the floating gate drive for the N-Channel MOSFET. The second charge pump output current opposes the pull down current of the slow turn-off transistor to provide regulation of the GATE voltage. The presence of the charge pump allows the use of an N-Channel MOSFET with a floating gate drive. The N-Channel MOSFETs normally have lower rDS(ON) (not to mention cost saving) compared to P-Channel MOSFETs, allowing further reduction of conduction losses.
VIN
GATE VIN VTH(HS) HV PASS AND CLAMP
VOUT COMP R1 R2 C2
2A*
+
HS DRIVER COMP
5.3V VSET BIAS
BIAS AND REF
Bias currents for the two internal zener supplies (HVREF and VSET) is provided by this block. This block also provides a 0.6V band-gap reference used in the UV detection circuit.
R1 + R2 = 50k
Undervoltage Comparator
FIGURE 2. HS COMPARATOR
The undervoltage comparator compares HVREF to 0.6V internal reference. Once it falls below this level the UV circuitry pulls and holds down the gate pin as long as the HVREF UV condition is present. Voltage at both VIN and HVREF pins track each other.
7
FN9131.3 February 15, 2007
ISL6144
High Voltage Pass and Clamp
A high voltage pass and clamping circuit prevents the high output voltage from damaging the comparators in case of quick drop in VIN. The comparators are running from the 5V supply between HVREF and VIN. These devices are rated for 5V and will be damaged if VOUT is allowed to be present (as the output is powered from other parallel supplies), and does not fall when VIN is falling. For example, if VIN falls to 30V, VOUT remains at 48V and the differential Voltage between the "-" and "+" terminals of the comparator would be 18V, exceeding the rating of the devices and causing permanent damage to the IC.
Application Considerations
ORing MOSFET Selection
Using an ORing MOSFET instead of an ORing diode results in increased overall power system efficiency as losses across the ORing elements are reduced. The use of ORing MOSFETs becomes more important at higher current levels, as power loss across the traditionally used ORing diode is very high. The high power dissipation across these diodes requires special thermal design precautions such as heat sinks and forced airflow. For example, in a 48V, 40A (1+1) redundant system with current sharing, using a Schottky diode as the ORing (auctioneering) device (Refer to Figure 5), the forward voltage drop is in the 0.4V to 0.7V range. Let us assume it is 0.5V, power loss across each diode is:
I OUT P loss ( D1 ) = P loss ( D2 ) = -------------- V F = 20A 0.5V = 10W 2 (EQ. 4)
Fault Detection Block
The fault detection block has two monitoring circuits (refer to Figure 4): 1. Gate monitoring detects when the GATE < VIN + 0.37V 2. VOUT monitoring detects when VIN - 0.41V > VOUT These two outputs are ORed, inverted, level shifted, and delayed using an internal filter (TFLT) The following failures can be detected by the fault detection circuitry: 1. ORing FET off due to dead short in the sourcing supply, leading to VIN < VOUT 2. Shorted terminals of the ORing FET 3. Blown fuse in the power path of the sourcing supply 4. Open Gate terminal 5. HVREF UV The FAULT pin is not latched off and the pull down will shut off as soon as the fault is removed and the pin becomes high impedance. Typically, an external pull-up resistor is connected to an external voltage source (for example 5V, 3.3V) to pull the pin high, an LED can be used to indicate the presence of a fault.
GATE + -
Total power loss across the two ORing diodes is 20W.
INPUT BUS 1 36VDC TO 75 VDC CIN1 100F Cd1 220nF DC/DC #1 +IN +OUT PC PR -IN +S SC -S -OUT SECONDARY GROUND +OUT2 = 48V Rpb2 10 (Note 8) Figure 15 D2 0.5V@ 20A D1 0.5V@ 20A
+OUT1 = 48V Rpb1 10 (Note 8) Figure 15
Ccs1 1nF
VOUT (40A)
INPUT BUS 2 36VDC TO 75 VDC CIN2 100F Cd2 220nF Ccs2 1nF
DC/DC #2
+IN +OUT PC PR -IN +S SC -S -OUT
FAULT
0.37V + +
PRIMARY GROUND VIN
FIGURE 4. 1 + 1 REDUNDANT SYSTEM WITH DIODE ORing
+ -
DELAY 120s LEVEL SHIFT
0.41V
VOUT
If a 5m single MOSFET per feed is used, the power loss across each MOSFET is:
I OUT 2 P loss ( M1 ) = P loss ( M2 ) = -------------- r DS ( ON ) 2 (EQ. 5)
FIGURE 3. FAULT DETECTION BLOCK P loss ( M1 ) = ( 20A ) 5m = 2W
2
Total power loss across the two ORing MOSFETs is 4W. In case of failure of current sharing scheme, or failure of DC/DC #1, the full load will be supplied by DC/DC #2. ORing
8
FN9131.3 February 15, 2007
ISL6144
MOSFET M2 or ORing Diode D2 will be conducting the full load current. Power loss across the ORing devices is:
P loss ( D2 ) = I OUT V F = 40A 0.5V = 20W P loss ( M2 ) = ( I OUT ) r DS ( ON ) = ( 40A ) 5m = 8W
2 2
(EQ. 6)
This shows that worst-case failure scenario has to be accounted for when choosing the ORing MOSFET. In this case we need to use two MOSFETs in parallel per feed to reduce overall power dissipation and prevent excessive temperature rise of any single MOSFET. Another alternative would be to choose a MOSFET with lower rDS(ON). The final choice of the N-Channel ORing MOSFET depends on the following aspects: 1. Voltage Rating: The drain-source breakdown voltage VDSS has to be higher than the maximum input voltage including transients and spikes. Also the gate to source voltage rating has to be considered, The ISL6144 maximum Gate charge voltage is 12V, make sure the used MOSFET has a maximum VGS rating >12V. 2. Power Losses: In this application the ORing MOSFET is used as a series pass element, which is normally fully enhanced at high load currents; switching losses are negligible. The major losses are conduction losses, which depend on the value of the on-state resistance of the MOSFET rDS(ON), and the per feed load current. For an N + 1 redundant system with perfect current sharing, the per feed MOSFET losses are:
I LOAD 2 P loss ( FET ) = ---------------- r DS ( ON ) N+1 (EQ. 7)
On the other hand, the most common failures caused by diode ORing include open circuit and short circuit failures. If one of these diodes (Feed A) has failed open, then the other Feed B will provide all of the power demand. The system will continue to operate without any notification of this failure, reducing the system to a single point of failure. A much more dangerous failure is where the diode has failed short. The system will continue to operate without notification that the short has occurred. With this failure, transients and failures on Feed B propagate to Feed A. Also, this silent short failure could pose a significant safety hazard for technical personnel servicing these feeds.
"ISL6144 + ORing FET" vs "Discrete ORing FET" Solution
If we compare the ISL6144 integrated solution to discrete ORing MOSFET solutions, the ISL6144 wins in all aspects. The main ones are: PCB real estate saving, cost savings, and reduction in the MTBF of this section of the circuit as the overall number of components is reduced. In brief, the solution offered by this IC enhances power system performance and protection while not adding any considerable cost. This solution provides both a PCB board real estate savings and a simple to implement integrated solution.
Setting the External HS Comparator Threshold Voltage
In general, paralleled modules in a redundant power system have some form of active current sharing, to realize the full benefit of this scheme, including lower operating temperatures, lower system failure rate, and better transient response when load step is shared. Current sharing is realized using different techniques; all of these techniques will lead to similar modules operating under similar conditions in terms of switching frequency, duty cycle, output voltage and current. When paralleled modules are current sharing, their individual output ripple will be similar in amplitude and frequency and the common bus will have the same ripple as these individual modules and will not cause any of the turn-off mechanisms to be activated, as the same ripple will be present on both sensing nodes (VIN and VOUT). This would allow setting the high speed comparator threshold (VTH(HS)) to a very low value. As a starting point, a VTH(HS) of 50mV could be used, the final value of this TH will be system dependant and has to be finalized in the system prototype stage. If the gate experiences false turn-off due to system noise, the VTH(HS) has to be increased. The reverse current peak can be estimated as:
V TH ( HS ) + V SD + V OS ( HS ) I reverseP = -----------------------------------------------------------------------r DS ( ON ) (EQ. 8)
The rDS(ON) value also depends on junction temperature; a curve showing this relationship is usually part of any MOSFET's data sheet. The increase in the value of the rDS(ON) over temperature has to be taken into account. 3. Current handling capability, steady state and peak, are also two important parameters that must be considered. The limitation on the maximum allowable drain current comes from limitation on the maximum allowable device junction temperature. The thermal board design has to be able to dissipate the resulting heat without exceeding the MOSFET's allowable junction temperature. Another important consideration when choosing the ORing MOSFET is the forward voltage drop across it. If this drop approaches the 0.41V limit, which is used in the VOUT fault monitoring mechanism, then this will result in a permanent fault indication. Normally the voltage drop would be chosen not to exceed a value around 100mV.
"ISL6144 + ORing FET" vs "ORing Diode" Solution
"ISL6144 + ORing FET" solution is more efficient, which will result in simplified PCB and thermal design. It will also eliminate the need for a heat sink for the ORing diode. This will result in cost savings. In addition, the ISL6144 solution provides a more flexible, reliable and controllable ORing functionality and protects against system fault scenarios (refer to "Fault Detection Block" on page 8). 9
where: VSD is the MOSFET forward voltage drop.
FN9131.3 February 15, 2007
ISL6144
VOS(HS) is the voltage offset of HS Comparator.
COMP CAPACITOR (C2) Placed between VOUT and COMP pins to provide filtering and decoupling. A 10nF capacitor is adequate for most cases.
The duration of the reverse current pulse is a few hundred nanoseconds and is normally kept well below current rating of the ORing MOSFET. Reducing the value of VTH(HS) results in lower reverse current amplitude and reduces transients on the common bus output voltage.
Protecting VIN and VOUT from High dv/dt Events
In hot swap applications where the ISL6144 is directly connected to a prebiased bus (thus exposing either the VIN or VOUT pins directly to high dv/dt transients), these pins must be filtered to prevent catastrophic damage caused by the high dv/dt transients. A simple RC filter using a series resistor, < 100 and the standard > 100nF decoupling capacitor to ground. This will give >1s rise time on the VIN pin to protect it. A resistor of the same value may be added to the other (VOUT) pin to eliminate the small HS Vth error introduced by that series R, ~0.45V at 48V with 100 resistor. Alternately the programmed HS Vth can be adjusted upward by that much as previously described.
.
HVREF and COMP Capacitor Values
HVREF CAPACITOR (C1) this capacitor is necessary to stabilize the HVREF(VZ) supply and a value of 150nF is sufficient. Increasing this value will result in gate turn-on time increase.
Typical Performance Curves and Waveforms
REG AMP FORWARD REGULATION (mV) 12 CHARGE PUMP VOLTAGE (V) 75V 11 12V 48V 32 75V 28 48V 24 10V AND 12V 20
10
9 10V 8
16
7 -40
-20
0
20
40
60
80
100
120
12 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 5. CHARGE PUMP VOLTAGE (VGQP) vs TEMPERATURE
FIGURE 6. REG. AMP FORWARD REGULATION
6.0 5.5 VSET VOLTAGE (V) BIAS CURRENT (mA) 5.0 4.5 4.0 3.5 3.0 2.5 2.0 -40 -20 0 20 40 60 80 100 120 12V 12V 10V 75V 48V
5.4
5.3
75V 48V 10V AND 12V
5.2
5.1
5.0 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
FIGURE 7. I BIAS CURRENT vs TEMPERATURE
FIGURE 8. VSET VOLTAGE
10
FN9131.3 February 15, 2007
ISL6144 Typical Performance Curves and Waveforms
6.000 75V 5.875 HVREF VOLTAGE (V) 48V 5.750 5.625 5.500 5.375 5.250 -40 10V AND 12V
(Continued)
HVREF(VZ) 1V/DIV VG 10V/DIV VIN 10V/DIV
IIN
10A/DIV
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
FIGURE 9. HVREF VOLTAGE
FIGURE 10. FIRST SUPPLY START-UP
rDS(ON) = 19m, QTOT = 70nC, EXTERNAL CGS = 33nF, VTH(HS) = 55mV IIN2 VOUT 10V/DIV VIN2 5A/DIV
rDS(ON) = 19m, QTOT = 70nC, EXTERNAL CGS = 33nF, VTH(HS) = 55mV IIN2 VOUT 10V/DIV VIN2 10V/DIV VGS2 5V/DIV 5V/DIV 5A/DIV
VGS2
10V/DIV
FIGURE 11. HIGH SPEED TURN-OFF, VIN = 48V, COMMON LOAD IS SMPS (CLOAD = 100F) WITH EQUIVALENT 4A LOAD
FIGURE 12. HIGH SPEED TURN-OFF, VIN = 48V, COMMON LOAD IS SMPS (CLOAD = 100F) WITH EQUIVALENT 1.3A LOAD
11
FN9131.3 February 15, 2007
Typical Performance Curves and Waveforms
IIN2 VOUT 2A/DIV
(Continued)
VOUT 10V/DIV VIN2 VIN2 10V/DIV VGS2 5V/DIV VGS2 5V/DIV IIN2 2A/DIV 2V/DIV
FIGURE 13. SLOW SPEED TURN-OFF, VIN = 48V, COMMON LOAD IS SMPS (CLOAD = 100F) WITH EQUIVALENT 4A LOAD
FIGURE 14. SLOW SPEED TURN-OFF, VIN = 12V, COMMON LOAD IS SMPS (CLOAD = 100F) WITH EQUIVALENT 4A LOAD
Application Circuit
INPUT BUS 1 36V TO 75VDC CIN1 100F DC/DC #1 +IN +OUT Cd1 220nF Ccs1 1nF PC PR -IN +S SC -S -OUT +OUT1 = 48V Rpb1 Sa Sb 10 FROM CB Cpb1 22F C1 150nF 5V R3 F1 15A D1 (NOTE 7) Q1 FDB3632 VIN GATE VOUT C2 R1 10nF 499 R2 47.5k
4.99k
HVREF U1 COMP ISL6144 VSET FAULT GND
COMMON BUS "CB" 10A
INPUT BUS 2 36V TO 75VDC CIN2 100F
DC/DC #2 +IN +OUT PC Ccs2 1nF PR -IN +S SC -S -OUT
+OUT2 = 48V Rpb2 Sa Sb 10 FROM CB Cpb2 22F
F2 15A
D2 (NOTE 7) Q2 FDB3632
Cd2 220nF
C3 150nF 5V R 4 4.99k
VIN
GATE
VOUT
U1 COMP HVREF ISL6144 VSET FAULT GND
R5 499 R6 47.5k
C4 10nF
PRIMARY
SECONDARY
NOTES: 11. D1, D2 are parasitic MOSFET diodes. 12. Remote Sense pin (+S) on both DC/DC converters has to be connected either directly at the module output (Sa closed) or to the CB point (Sb closed). Connecting to CB is not recommended as it might cause Fault propagation in case of short circuit on a PS output. 13. F1, F2 are optional and can be eliminated depending on power system configuration and requirements. 14. DC/DC #1, 2 configuration is based on Vicor V48B48C250AN3. FIGURE 15. APPLICATION CIRCUIT FOR A 1 + 1 REDUNDANT 48V SYSTEM
12
FN9131.3 February 15, 2007
ISL6144 Using the ISL6144EVAL1 High Voltage ORing MOSFET Controller Evaluation Board
In a multiple supply, fault tolerant, redundant power distribution system, paralleled power supplies contribute equally to the load current through various power sharing schemes. Regardless of the scheme, a common design practice is to include discrete ORing power diodes to protect against reverse current flow should one of the power supplies develop a catastrophic output short to ground. In addition, reverse current can occur if the current sharing scheme fails and an individual power supply voltage falls significantly below the others. Although the discrete ORing diode solution has been used for some time and is inexpensive to implement, it has some drawbacks. The primary downside is the increased power dissipation loss in the ORing diodes as power requirements for systems increase. In some systems this lack of efficiency results in a cost that surpasses the cost of the ISL6144 and power FET implementation. The power loss across a typical ORing diode with 20A is about 10W. Many diodes will be paralleled to help distribute the heat. In comparison, a FET with 5m on-resistance dissipates 2W, which constitutes an 80% reduction. When multiplied by the number of paralleled supplies, the power savings are significant. Another disadvantage when using an ORing diode would be failure to detect a shorted or open ORing diode, jeopardizing power system reliability. An open diode reduces the system to a single point of failure while a diode short might pose a hazard to technical personnel servicing the system while unaware of this failure. The ISL6144 ORing MOSFET Controller and a suitably sized N-Channel power MOSFET(s) increase power distribution efficiency and availability when replacing a power ORing diode in high current applications. It can be used in +10V to +75V systems and has an internal charge pump to provide a floating gate drive for the N-Channel ORing MOSFET. The input/output differential trip point "VOUT - VIN" can be programmed by two external resistors (R1, R2 or R6, R7). This trip point can be adjusted to avoid false gate trip off due to power supply noise. The high speed comparator action protects the common bus from being affected due to individual power supply shorts by turning off the ORing MOSFET of the shorted feed in less than 300ns (when using an ORing MOSFET with equivalent gate to source capacitance equal to 39nF). The Hysteretic Regulating (HR) Amplifier provides a slow turn-off of the ORing MOSFET. This turn-off is achieved in less than 100s when one of the sourcing power supplies is shutdown slowly for system diagnostics, ensuring zero reverse current. This slow turn-off mechanism also reacts to output voltage droop, degradation, or power-down. 13
FN9131.3 February 15, 2007
A circuit fault condition is indicated on an open drain FAULT pin. The fault detection circuitry covers different types of failures; including dead short in the sourcing supply, a deadshort of any two ORing MOSFET terminals, or a blown fuse in the power distribution path.
Typical Application
PS_1 VIN1 10V TO 75V DC/DC C5* 1 GATE VPU C1 R3 LED1 CS RED FAULT GND VSET VIN VOUT U1 ISL6144 COMP HVREF Q1 C6* R1 C2
PS_2
VIN2 10V TO 75V DC/DC C7* 2 VPU R4 C3 LED2 GATE
Q1 C8* VOUT U2 ISL6144 HVREF COMP VIN VSET R6 C4 R7 FAULT GND
RED R1 = R6 = 499 (5%) R2 = R7 = 47.5k (5%) R3 = R4 = 1.21k (5%)
C1 = C2 = 150nF (10V) C3 = C4 = 10nF (10V) C5* TO C8* = 100nF *(100V) Optional Decoupling Caps
- LED1, LED2 are red LEDs to indicate a fault, different interfaces are possible to the FAULT pin. - VPU is an external pull up voltage source. Also, VOUT can be used as the pull up source. In this case if it is higher than 16V, use a zener diode from the FAULT pin to GND with a clamping voltage less than the rating of the FAULT pin which is 16V.
Related Literature
* TB389 (PCB Land Pattern Design and Surface Mount Guidelines for QFN (MLFP) Packages) * Manufacturer's MOSFET data sheets
COMMON BUS
R2
VOUT
ISL6144
DC/DC CONVERTERS (NOT PART OF THE EVAL BOARD) ISL6144EVAL1 CONTROL BOARD
FIGURE 16. TEST SETUP USING DC/DC MODULES
ISL6144 Evaluation Board Overview
This section of the datasheet serves as an instruction manual for the ISL6144EVAL1 board. It also provides design guidelines and recommendations for using the ISL6144 for ORing MOSFET control. The ISL6144EVAL1 Control Board has two parallel feeds connected to each other through N-channel ORing MOSFETs. Each ORing MOSFET has an ISL6144 connected to it. This board demonstrates the operation of Intersil's ISL6144 HV ORing MOSFET Controller IC in a typical 1 + 1 redundant power system. To demonstrate the functionality of the ISL6144, two power supplies with identical output voltages are required as the input to the ISL6144EVAL1 board. This will show the ability of the ISL6144 to provide the gate drive voltage for the ORing N-Channel MOSFET. The ISL6144 also monitors the drain (VOUT), source (VIN) and gate voltages in order to provide reverse current protection and protection against power feeds' related faults. Figure 17 shows a test setup used in the characterization of ISL6144 in a 1 + 1 redundant power system.
other). ORing MOSFET's gate drive voltage, control and monitoring for each of these feeds are implemented using the ISL6144. The board has the following features: * Evaluation of the ISL6144 in a 1 + 1 redundant power system using a single board * Has footprint for a total of three parallel MOSFETs per feed. Number of MOSFETs used will depend on the load current (on the standard ISL6144EVAL1 board only one MOSFET is populated per feed) * Allows the user to test turn-on, slow turn-off, fast turn-off and different fault scenarios * Visual fault indication with Red LEDs * Banana Connectors and test points for all inputs, outputs and IC pins * Can be easily connected to the power system prototype for initial evaluation Note that the board was designed to handle high load currents (up to 20A per feed) with the appropriate MOSFET selection.
ISL6144EVAL1 Control Board (Rev C)
This board is configured with two input power feeds connected in parallel for redundancy using ORing MOSFETs. The ISL6144 allows the two rails to operate in active ORing mode (This means that both feeds can share the current if their respective voltages are close to each
14
FN9131.3 February 15, 2007
ISL6144 Input Voltage Range (+10V to +75V)
The ISL6144 can operate in equipment with voltages in the +10V to +75V range. The ISL6144 can also be used in systems with negative voltages -10V to -75V, but it has to be placed on the return (high) side. For example, in ATCA systems, an ORing of both the low (-48V) and high (-48V Return) sides is required. In this case the ISL6144 can be used on the high side. The ISL6144 draws bias from both the input and output sides. External bias voltage rail is not needed and cannot be used. As soon as the Input voltage reaches the minimum operational voltage, the internal charge pump turns on and provides gate voltage to turn-on the ORing FET. (depending on the output capacitance value of the power supply/module, a local loading resistor might be needed to help discharge the BPS output capacitor). An output capacitor COUT (equivalent to the capacitor that will be used in the final power system solution) is connected to the Common Bus point (VOUT). Different types of loads can be used (power resistors, electronic load or simply another DC/DC converter).
AUX PS* + 5V + PS1 +48V + PS2 +48V PS2_V2RTN BENCH POWER SUPPLIES PS2_V2 = VIN2 VIN2 J8 GND ISL6144EVAL1 CONTROL BOARD PS1_V1RTN USED ONLY FOR POWERING THE LEDS PS1_V1 = VIN1 QSHORT J4 VIN1 J6 GND J7 J2 VOUT J3 GND L COUT O A D
J1 5V_AUX
Multiple Feed ORing (ISL6144EVAL1)
In today's high availability systems, two or more power supplies can be paralleled to provide redundancy and fault tolerance. These paralleled power supplies operate in an active ORing mode where all of these supplies share the load current, depending on the redundancy scheme implemented in the particular system. The power system must be able to continue its normal operation, even in the event of one or more failures of these power supplies. Faults occurring on the power supply side need to be isolated from the common bus point connected to the system critical loads. This fault isolation device is known as the ORing device. The function of the ORing device is to pass the forward supply current flowing from the power supply side and block the reverse fault current. A fault current might flow if a short occurs on the input side (typically this could be a power supply output capacitor short). In this case, the input voltage drops and current may flow in the reverse direction from the load to the input, causing the common bus to drop and the system to fail. Although ORing diodes are simple to implement in such systems, they suffer from many drawbacks, as outlined earlier. The ISL6144 (with an external N-Channel MOSFET) provides an integrated solution to perform the ORing function in high availability systems, while increasing power system efficiency at the same time.
* Auxiliary power supply is used to power the LED circuit. If VOUT is less than 16V, J1 can be connected directly to VOUT (J5). If VOUT is higher than 16V, we still can use VOUT to replace AUX PS, but a zener diode has to be connected from FAULT to GND to clamp the voltage across the pin to 16V or lower. FIGURE 17. TEST SETUP USING BENCH PS
Option 2: Using a custom designed DC/DC converter Power Board which consists of two DC/DC modules connected in current sharing configuration, each DC/DC module output can be turned off slowly using the ON/OFF pin or can be shorted using on-board Power MOSFET (Refer to Figure 19). In this case also, similar considerations for COUT and type of load apply as in option 1 above.
AUX PS + + PS1 +48V PS2_V2 + PS2 +48V BENCH POWER SUPPLIES PS1_V1 J1
PS1_V1RTN
USED ONLY FOR POWERING THE LEDs
J4 VOUT1 DC/DC 1 J6 J2 PRI_GND GND CS J7 J3 VOUT2 DC/DC 2 J8 J9 PRI_GND GND
J4
J1 VIN1 5V_AUX J6 GND J7 VIN2 J8 GND ISL6144EVAL1 CONTROL BOARD J2 VOUT J3 GND
L COUT O A D
Operating Instructions and Functional Tests
Test setup for ISL6144EVAL1 is shown in Figures 17 and 18 with two options for the input power sources. Option 1: Using two identical bench power supplies (BPS) connected directly to the ISL6144EVAL1 Control Board (refer to Figure 18). Just make sure to program the voltages on PS1_V1 and PS2_V2 to identical values so that they share the load current. A MOSFET (Qshort) is connected at the Input of one or both feeds as close as possible to the input connectors of the ISL6144EVAL1 board. Slow turn-off of the input BPS can be performed by the on/off button
PS2_V2RTN
POWER MODULES BOARD*
* Power Modules Board can be replaced by bench power supplies or any discrete DC/DC modules. Just make sure to adjust both VOUT1 and VOUT2 close to each other to allow current sharing between the two modules (Refer to option 1 and Figure18). FIGURE 18. TEST SETUP USING DC/DC MODULES
15
FN9131.3 February 15, 2007
ISL6144
DC/DC Converter Power Board (not part of the ISL6144EVAL1 board)
The DC/DC converter board consists of two DC/DC converters with independent input voltage rails. In reality, two identical power supplies can be used in the test setup to replace this board (Contact Intersil Applications Engineering if you need assistance in your test setup). This DC/DC converter board is configured for operation at different output voltage levels depending on the choice of DC/DC modules. Most evaluation results are provided for a mix of +48V and +12V input voltages. Any other voltage within the +10V to +75V range can also be used. Each DC/DC converter has a low rDS(ON) MOSFET connected in parallel to the output terminals. This MOSFET is normally off. When turned on it simulates a short across the output. Another MOSFET is connected at the ON/OFF pin of the modules to simulate a slow turn-off of the module.
Two Feed Parallel Evaluation
Two Feed parallel operation verification can be performed after completion of the single feed evaluations. Make sure that the two Input power supplies connected to the ISL6144EVAL1 board are identical in voltage value. Identical input voltages are needed to enable the two feeds to share the load current (In real world power systems, current sharing is most likely insured by the power supplies/modules that have an active current sharing feature). 1. Turn-on PS1 and PS2 in sequence (hot plugging is not recommended). Adjust VIN1 and VIN2 close to each other. Verify the input current of both feeds to be within acceptable current sharing accuracy (~10%). Current sharing accuracy will be very poor at light loads and becomes better with higher load currents. 2. Adjust the load current to different values and verify that both VSD1 (TP1 to TP2) and VSD2 (TP4 to TP5) are close to each other. These two voltages might be different depending on the amount of load current passing through each of the two feeds. 3. At light loads, ILoad * rDS(ON) is less than 20mV, the ISL6144 operates in the forward regulation mode and gate voltage is modulated as a function of load current. When ILoad*rDS(ON) becomes higher than the regulated 20mV, the charge pump increases and clamps the gate voltage to the maximum possible charge pump voltage, VGQP. 4. Verify the Gate voltage of both MOSFETs VGS1 (TP13 to TP17) and VGS2 (TP14 to TP21) with different load currents. 5. Both LED1 and LED2 are off when both feeds are on. 6. For ILoad = 4A, turn-off VIN2 and note that VGS2 has turned off. LED2 is RED and VGS1 has increased from around 4V to VGQP. 7. Turn VIN2 back on and turn VIN1 off. VGS1 is now off. LED1 is RED. VGS2 has increased to VGQP.
Single Feed Evaluation
The ISL6144EVAL1 is hooked up to two input power supplies using test setup shown in Figure 18 or Figure 19. Note that the ISL6144EVAL1 is populated with one FDB3632 MOSFET per feed (Nominal value of the MOSFET's rDS(ON) is approximately 8m at VGS = 10V). 1. Connect the input power supplies, auxiliary 5V power supply, load and output capacitor to the ISL6144EVAL1. 2. Connect test equipment (Oscilloscope, DMM) to the signals of interest using on-board test points and scope probe jacks. 3. Turn-on PS1 with VIN1 = +48V (VIN1 can be any voltage within +10V to +75V). Turn-on the auxiliary power supply (AUX PS powering the LED circuit) with +5V. Adjust load current to 2A. Verify the main operational parameters such as the 20mV forward regulation at light loads, and gate voltage as a function of load current. 4. The forward voltage drop across the MOSFET terminals VSD1 (TP1-TP2) is equal to the maximum of the 20mV forward regulated voltage drop across the source-drain "VFWD_HR" or the product of the load current and the MOSFET on-state resistance "ILoad * rDS(ON)". 5. For ILoad = 2A, VSD1 is equal to VFWD_HR = 20mV. The gate-source voltage is modulated as a function of load current and MOSFET transconductance. Gate-source voltage VGS1 (TP13 -TP17) is approximately 4V. In this case, LED1 is off. LED2 will be RED as VIN2 is still off. 6. Increase the load current ILoad to 4A. Note that VDS1 is increased to above VFWD_HR and operation in the 20mV forward regulation cannot be maintained. The MOSFET cannot deliver the required load current with a 20mV constant VSD1. In this case, gate voltage is fully chargepumped to VGQP (10.6V nominal). 7. Turn-off VIN1 and turn-on VIN2 and repeat the same tests listed above. Make sure the ISL6144 is providing gate voltage, which is modulated based on the load current. VSD2 is measured between (TP4-TP5), VGS2 is measured between (TP14-TP21). 16
Performance Tests
Performance tests can be carried out after the two feeds have been verified and found to be operational in active, 1 + 1 redundancy (when two feeds share the load current, current sharing is ensured by the incoming power supplies.) These include gate turn-on at power supply start-up, fast speed turn-off (in case of fast dropping input rail), slow speed turn-off (in response to slow dropping input rail) and fault detection in response to different faults.
Gate Start-Up Test
FIRST FEED START-UP When the first feed is turned on, as VIN1 rises, conduction occurs through the body diode of the MOSFET. This only occurs for a short time until the MOSFET gate voltage can be charge-pumped on. This conduction is necessary for proper operation of the ISL6144. It provides bias for the gate hold off and other internal bias and reference circuitry. The
FN9131.3 February 15, 2007
ISL6144
charge pump circuitry starts functioning as the input voltage at the VIN pin reaches a value around 8V. The gate voltage depends on the load current (as explained in previous sections), The maximum gate voltage will be clamped to a maximum of VGQP when load current becomes too high to be handled with 20mV across the source-drain terminals. Overall, it takes less than 1ms to reach the load-dependant final gate voltage value. Note that the Input voltage cannot be hot swapped and has to rise slowly. A rise time of at least one ms is recommended for the voltage at VIN pin.
VIN = 48V; RESISTIVE LOAD = 4A, CGSEXT = 33nF VIN1,VG1,IIN1 and HVREF(VZ) WAVEFORMS HVREF(Vz) 5V/DIV IIN1 2A/DIV 4A VIN = 12V; RESISTIVE LOAD = 5A, CGSEXT = 33nF IIN1 5A/DIV VG1 5V/DIV
VIN1 5V/DIV VOUT 5V/DIV
0A
VG1 10V/DIV
FIGURE 20. FIRST FEED VIN1 START-UP (12V CASE)
VIN1 10V/DIV
The start-up tests were done with the addition of an external gate to source capacitor to demonstrate start-up time with a total equivalent gate-source capacitance around 39nF. SECOND (CONSECUTIVE) FEED START-UP
WHEN VIN REACHES ~ 8V AND HVREF REACHES 3V to 4V, GATE CHARGE PUMP ACTION STARTS
VIN1, VG1, IIN1 and VOUT WAVEFORMS
0A
IIN1 5A/DIV
4A
VOUT 20V/DIV
In this case, the ISL6144 for the second (consecutive) feed (U4) already has output bias voltage as the first parallel feed has been turned on and VOUT is present on the common bus. As VIN2 rises, VG2 rises with it (VG2 is GATE2 voltage with respect to GND). When VIN2 approaches VIN1 value, Gate 2 is turned. Second feed gate turn-on is faster than the first feed as the HVREF capacitor (C3) is already charged.The second or consecutive power supply to be started can be turned on faster than the first power supply, a rise time of at least 200s of the second rail is recommended.
VIN = 48V; RESISTIVE LOAD = 4A, CGS(EXT) = 33nF
VG1 20V/DIV
IIN2 2A/DIV
VIN1 20V/DIV WHEN VIN REACHES ~ 8V AND HVREF REACHES 3V TO 4V GATE CHARGE PUMP ACTION STARTS
VOUT 20V/DIV
IN THIS CASE GATE VOLTAGE IS MEASURED BETWEEN GATE2 AND GND VG2 SECOND GATE TURNS ON ONLY WHEN VIN2 REACHES VIN1 20V/DIV VIN2 20V/DIV
FIGURE 19. FIRST FEED VIN1 START-UP (48V CASE)
POWER SUPPLY RELATED DELAY
FIGURE 21. SECOND (CONSECUTIVE) FEED VIN2 START-UP
17
FN9131.3 February 15, 2007
ISL6144 Gate Fast Turn-off Test
During normal operation, the ISL6144 provides gate drive voltage for the ORing MOSFET when the Input voltage exceeds the output voltage. The current flows in the forward direction from the input to the output. Now, what happens if the input voltage drops quickly below the output voltage as a result of a failure on the input sourcing power supply while the MOSFET remained on? The answer is: If the MOSFET is kept on, current starts to flow in the reverse direction from the output to the input. Of course this is not desired nor acceptable. It will lead to effectively shorting the output and causing an overall system failure. In order to block this reverse current, the ISL6144 senses the voltage at both VIN and COMP pins (this is VOUT voltage reduced by a resistor programmable threshold (VTH(HS), it is programmed to 55mV on the EVAL board and could be adjusted by changing R1, R4 values for both feeds. If VIN drops below COMP (VOUT - VTH(HS), the High Speed Comparator turns off the gate of the ORing MOSFET very quickly, the gate pull down current IPDH is 2A. As a result the reverse current flow is prevented. The maximum turn-off time is less than 300ns when using an ORing MOSFET(s) with an equivalent gatesource capacitance of 39nF (equivalent to QTOT = 390nC at VGS = 10V). On the ISL6144EVAL1 board, FDB3632 has an equivalent gate-source capacitance of 8.4nF, some of the tests are performed while an external gate to source capacitance is added to demonstrate gate current sink capability.
VIN1 = VIN2 = 48V; RESISTIVE LOAD = 4A, CGS(EXT) = 0nF VG2 10V/DIV
tDELAY(HS) is the High Speed Comparator internal worstcase time delay. The setup in Figure 18 can be used to perform the Input dead-short test; a pulse generator is connected between Gate-Source of QSHORT1 (use pulse mode single shot, set the frequency to <10Hz and pulse width of approximately 10ms, tRISE = 1s). Follow steps 1 through 5 in the two feed parallel operation section. Make sure that both feeds operate in parallel current sharing mode. Proceed with the short test by applying the single pulse to the gate of QSHORT1. Once turned on, QSHORT1 shorts VIN1 causing it to fall quickly (in less than 10s). Figures 23, 24 and 25 show the results for different combinations of CGS1 and load current. Make sure to connect the VIN1 shorting-MOSFET terminals as close as possible to the VIN-GND (J4 to J6) terminals on the EVAL board to minimize lead impedance and reduce parasitic ringing.
VIN1 = VIN2 = 48V; RESISTIVE LOAD = 6A, Cgs(ext) = 33nF
IIN1 2A/DIV
REVERSE CURRENT
VOUT 10V/DIV VIN1 10V/DIV
VGS1 5V/DIV
0.1s/DIV
IIN1 2A/DIV
VOUT 10V/DIV
FIGURE 23. FAST SPEED TURN-OFF (MOSFET WITH QTOT = 8.4nc) AND 33nF EXTERNAL CGS
VGS1 2V/DIV
REVERSE CURRENT DISSAPPEARS WHEN GATE IS COMPLETELY OFF
IIN1 2A/DIV
VIN1 = VIN2 = 48V; RESISTIVE LOAD = 6A, Cgs(ext) = 33nF
0.1s/DIV
VG2 10V/DIV VOUT 10V/DIV
FIGURE 22. FAST SPEED TURN-OFF (MOSFET WITH QTOT = 8.4nc)
Worst-case turn-off time can be calculated as:
V GS t toff ( WC ) = t DELAY ( HS ) + C GS ------------ I PDH 12V t toff ( WC ) = 50ns + 39nF ---------- = 284ns 2A
VGS1 5V/DIV
0.1s/DIV
(EQ. 9) FIGURE 24. FAST SPEED TURN-OFF (MOSFET WITH QTOT = 8.4nc) AND 33nF EXTERNAL Cgs
18
FN9131.3 February 15, 2007
ISL6144
The ISL6144EVAL1 board has VTH(HS) of 55mV. It can be changed if performance is found to be unacceptable with this value. VTH(HS) can affect the amplitude of the reverse current (short pulse) that might flow before the gate is effectively turned off (details on how to select VTH(HS) is included in a later section of this application note). The rDS(ON) and internal HS comp offset also contribute to the amplitude of the reverse current pulse. A short event on a single feed may cause ringing on the ground pins, the VIN, and on the VOUT pins. This ringing may cause false turn-off on the healthy feeds. Using decoupling capacitors both at the VIN and VOUT pins help in filtering this high frequency ringing and prevent false turn-off of parallel feeds. Figure 25 shows that the gate of second feed VG2 (measured with respect to ground) is not affected when feed 1 input is shorted. Input Voltage is falling at a slow rate (Figure 26, top scope shot shows a 20ms fall time for the input voltage). VOUT (Common Bus) remains almost unchanged at around 48V. It drops by a value equivalent to the increase in the portion of the load current passing through the remaining feed multiplied by the MOSFET's rDS(ON). At the beginning of the slow turn-off, the gate drive Voltage VGS1 (measured between the Gate and Source of the ORing MOSFET using a differential probe) starts to drop at a slower rate. This is attributed to the effect of the 20s filtering-delay. Afterwards a stronger pull down current starts and finally the high-speed turn-off completes the gate turnoff. Current through the turned off feed is also shown to be positive and the turn-off is complete with no reverse current. Figure 26 shows the same slow turn-off for a 12V input voltage case.
VIN1 = VIN2 = 12V
Power Supply Slow Turn-off
In many cases, a single power feed is turned off for diagnosis, maintenance or replacement. The Input voltage drops slowly (most probably in few ms). When voltage at VIN pin starts dropping with respect to VOUT pin. The Hysteretic Regulating Amplifier starts pulling down current (IPDL) opposite to the charge pump current. This reduces the gate voltage gradually until the MOSFET is completely turned off. The slow turn-off is accomplished with zero reverse current. An internal 20s delay filters out any false trip off due to noise or glitches that might be present on the supply line. The slow speed turn-off mechanism is shown in Figure 25:
VIN1 = VIN2 = 48V IIN2 VOUT
5ms/DIV ZOOMED IN VIEW
VGS2
VIN2
VOUT 2V/DIV VIN1 2V/DIV
VGS1 (DIFF PROBE) 5ms/DIV 5V/DIV
ZOOMED IN VIEW IIN2 2A/DIV VOUT 10V/DIV
IIN1 2A/DIV VIN2 10V/DIV VGS2 5V/DIV 20s/DIV
FIGURE 26. SLOW SPEED TURN-OFF (CGSTOT = 8.4nF + 33nF)
20s/DIV
FIGURE 25. SLOW SPEED TURN-OFF (CGSTOT = 8.4nF + 33nF)
19
FN9131.3 February 15, 2007
ISL6144 Detection of Power Feed Faults
The ISL6144 have two built-in mechanisms that monitor voltages at VIN, VOUT and GATE pins. The first mechanism monitors GATE with respect to VIN (with a 410mV threshold) and the second mechanism monitors VIN with respect to VOUT (with 370mV threshold). The open-drain FAULT pin will be pulled low when any of the two above conditions is met. Some of the typical system faults detected by the ISL6144 are:
Fault 3: MOSFET Gate to Source Dead Short
GATE voltage will be equal to VIN, GATE VIN = 12V, FAULT PULLED TO +5V
VG1 5V/DIV
FAULT 5V/DIV
VIN1 5V/DIV VOUT 5V/DIV
Fault 1: Open Fuse at the Input Side
(Fuse has to be placed before the VIN tap, between the power supply and the source of the ORing MOSFET), note that the EVAL board does not have footprint for installing this fuse. This feature can be tested by adding a fuse externally. The open fuse results in near zero current flow through the ORing MOSFET, only a very low current drawn by the IC bias will flow. The voltage at VIN pin is effectively disconnected from the power source and will start dropping slowly. The regulated source-drain voltage falls below its 20mV level and the gate of the MOSFET is pulled down and turned off. GATE will become low and a fault is indicated with internal built in delay (tFLT).
TIME SCALE 100s/DIV
FIGURE 28. MOSFET GATE TO SOURCE FAULT
Fault 4: ORing FET Off Condition
When VIN < VOUT, the Gate is off to block reverse current flow. This means that if an ORing feed is not sharing current, a fault will be indicated. Also if a feed (PS) is off while bias is applied from VOUT to that feed, then a fault is also indicated.
Fault 2: Drain to Source Short
In this case VIN is shorted to VOUT, and in theory the voltage drop across the shorted MOSFET terminals will be close to 0V. The Gate will be pulled down and a fault will be indicated. The resistance of the Drain to Source short multiplied by the Drain short current must be low enough to result in VSD< VFWD_HR (refer to data sheet for worst case values), Otherwise this fault cannot be detected.
VIN = 12V, FAULT PULLED TO +5V
Fault 5: MOSFET Gate to Drain Dead Short
In this case, the following condition will be violated GATE VIN = 12V, FAULT PULLED TO +5V
VG1 5V/DIV
FAULT 5V/DIV
VG1 5V/DIV
FAULT 5V/DIV
VIN1 5V/DIV VOUT 5V/DIV VOUT 5V/DIV
VIN1 5V/DIV
TIME SCALE 100s/DIV
TIME SCALE 100s/DIV
FIGURE 29. MOSFET GATE TO DRAIN FAULT FIGURE 27. MOSFET DRAIN TO SOURCE FAULT
20
FN9131.3 February 15, 2007
ISL6144
Fault 6: ORing FET Body Diode Conduction
(VIN - 0.41V > VOUT). If the voltage drop across the MOSFET approaches 410mV, a fault will be indicated. Make sure the selection of the ORing MOSFET takes this fact into account. For example, in a 48V, 32A (1 + 1) redundant system with current sharing, using a Schottky diode as the ORing device (Refer to Figure 31), the forward voltage drop is in the 0.4V to 0.7V range, (let us assume it is 0.5V). The power loss across each diode is shown in Equation 10:
I OUT P loss ( D1 ) = P loss ( D2 ) = -------------- V F = 16A 0.5V = 8W 2 (EQ. 10)
Application Considerations and Component Selection
"ISL6144 + ORing FET" vs "ORing Diode" Solution
"ISL6144 + ORing FET" solution is more efficient than the "ORing Diode" Solution, which will result in simplified PCB and thermal design. It will also eliminate the need for a heat sink for the ORing diode. This will result in cost savings. In addition is the fact that the ISL6144 solution provides a more flexible, reliable and controllable ORing functionality and protects against system fault scenarios (Refer to the fault detection block description.) On the other hand the most common failures caused by diode ORing include open circuit and short circuit failures. If one of these diodes (Feed A) has failed open, then the other Feed B will provide all of the power demand. The system will continue to operate without any notification of this failure, reducing the system to a single point of failure. A much more dangerous failure is where the diode has failed short. The system will continue to operate without notification that the short has occurred. With this failure, transients and failures on Feed B propagate to Feed A. Also, this silent short failure could pose a significant safety hazard for technical personnel servicing these feeds.
The total power loss across the two ORing diodes is 16W.
INPUT BUS 1 D1 0.5V@ 16A VOUT (32A) D2 0.5V @ 16A
DC/DC 1 CS
+IN1 = 48V
INPUT BUS 2
DC/DC 2
+IN2 = 48V
FIGURE 30. 1 + 1 REDUNDANT SYSTEM WITH DIODE ORING
If we use a 4.5m MOSFET (refer to Figure 32), the nominal Power loss across each MOSFET is:
I OUT 2 P loss ( M1 ) = P loss ( M2 ) = -------------- r DS ( ON ) 2 P lossNOM ( M1 ) = ( 16A ) 4.5m = 1.152W
2
(EQ. 11)
The total power loss across the two ORing MOSFETs is 2.304W. In case of failure of current sharing scheme, or failure of DC/DC 1, the full load will be supplied by DC/DC 2. ORing MOSFET M2 or ORing Diode D2 will be conducting the full load current. Power lost across the ORing devices are:
P lossMAX ( D2 ) = I OUT V F = 32A 0.5V = 16W
2 2
"ISL6144 + ORing FET" vs "Discrete ORing FET" Solution
If we compare the ISL6144 integrated solution to discrete ORing MOSFET solutions (with similar performance parameters), the ISL6144 wins in all aspects, the main ones being simplicity of an integrated solution, PCB real estate saving, cost savings, and reduction in the MTBF of this section of the circuit as the overall number of components is reduced. In brief, the solution offered by this IC enhances power system performance and protection while not adding any considerable cost, on the contrary saving PCB board real estate and providing a simple to implement integrated solution.
(EQ. 12)
P lossMAX ( M2 ) = ( I OUT ) r DS ( ON ) = ( 32A ) 4.5m = 4.6W (EQ. 13)
M1 4.5m 0.072V @ 16A
INPUT BUS 1
DC/DC 1
+IN1 = 48V
VOUT (32A) CS M2 4.5m 0.072V@ 16A +IN2 = 48V
ORing MOSFET Selection
Using an ORing MOSFET instead of an ORing diode results in increased overall power system efficiency as losses across the ORing elements are reduced. The benefit of using ORing MOSFETs becomes even more significant at higher load currents as power loss and forward voltage drop across the traditionally used ORing diode is increased. The high power dissipation across these diodes requires paralleling of many diodes as well as special thermal design precautions such as heat sinks (heat dissipating pads) and forced airflow. 21
INPUT BUS 2
DC/DC 2
FIGURE 31. 1+1 REDUNDANT SYSTEM WITH MOSFET ORING
FN9131.3 February 15, 2007
ISL6144
This shows that worst-case failure scenario has to be accounted for when choosing the ORing MOSFET. In both cases, more than one ORing MOSFET/diode has to be paralleled on each feed. Using parallel devices reduces power dissipation per device and limits the junction temperature rise to acceptable safe levels. Another alternative is to choose a MOSFET with lower rDS(ON) (Refer to Table 1 and Table 2 for some examples). If parallel MOSFETs are used on each feed, make sure to use the same part number. Also it is preferable to have parts from the same lot to insure load sharing between these paralleled devices. The final choice of the N-Channel ORing MOSFET depends on the following aspects: * Voltage Rating: The drain-source breakdown voltage VDSS has to be higher than the maximum input voltage, including transients and spikes. Also, the gate to source voltage rating has to be considered. The ISL6144 maximum Gate charge voltage is 12V. Make sure the used MOSFET has a maximum VGS rating >12V. * Power Losses: In this application, the ORing MOSFET is used as a series pass element, which is normally fully enhanced at high load currents. Switching losses are negligible. The major losses are conduction losses, which depend on the value of the on-state resistance of the MOSFET rDS(ON), and the per feed load current. For an N + 1 redundant system with perfect current sharing, the per feed MOSFET losses are:
I LOAD P loss ( FET ) = ---------------- r DS ( ON ) N+1
2
Suppose PLoss = 1W in a D2PAK MOSFET, junction to ambient thermal resistance RJA = +43C/W (with 1 inch2 copper pad area), TJMAX = +175C, rDS(ON) = 4.5m, maximum ambient board temperature = +85C. We need to make sure that the MOSFET's junction temperature during operation does not exceed the maximum allowable device junction temperature. TJ = TA_max + PLoss * RJA TJ = +85C+1W. +43C/W = +128C TJ < TJMAX In the example of Figure 32 with a load of 32A, at least 3 MOSFETs with rDS(ON) = 4.5m are paralleled to limit the dissipation to below 1W and operate with safe junction temperature. The following tables show MOSFET selection for some typical applications with different input voltages and load currents in a 1 + 1 redundant power system (a maximum of 1W of power dissipation across each MOSFET is assumed). For a 48V Input:
TABLE 1. INPUT VOLTAGE = 48V ILoad_Max 8A 16A MOSFET PART NUMBER FDB3632 (Note 8) SUM110N10-08 (Note 9) FDB3632 (Note 8) SUM110N10-08 FDB045AN08A0 (Note 10) FDB3632 (Note 8) SUM110N10-08 FDB045AN08A0 N (Note 7) 1 1 2 2 1 4 4 3
(EQ. 14) 32A
* The final MOSFET selection has to be based on the worse case current when the system is reduced to N parallel supplies due to a permanent failure of one unit. The remaining units have to provide the full load current. In this case, losses across each remaining ORing MOSFET become:
I LOAD 2 P loss ( FET ) = ---------------- r DS ( ON ) N (EQ. 15)
NOTES: 7. Number of parallel MOSFETs per feed 8. VDSS = 100V;ID = 80A; rDS(ON) = 9m 9. VDSS = 100V; ID = 110A; rDS(ON) = 9.5m 10. VDSS = 75V; ID = 80A; rDS(ON) = 4.5m
* In the particular cases illustrated in the previous examples of Figures 31 and 32 with N = 1, each of the two ORing feeds have to be able to handle the full load current. * The MOSFET's rDS(ON) value also depends on junction temperature; a curve showing this relationship is usually part of any MOSFET's data sheet. The increase in the value of the rDS(ON) over-temperature has to be taken into account. * Current handling capability, steady state and peak, are also two important parameters that must be considered. The limitation on the maximum allowable drain current comes from limitation on the maximum allowable device junction temperature. The thermal board design has to be able to dissipate the resulting heat without exceeding the MOSFET's allowable junction temperature.
For a 12V to 24V Input:
TABLE 2. INPUT VOLTAGE = 12V TO 24V ILoad_Max 15A MOSFET PART NUMBER IRF1503S (Note 11) SUM110N03-03P (Note 12) STB100NF03L-03 (Note 13) IRF1503S SUM110N03-03P STB100NF03L-03 N 1 1 1 2 2 2
40A
NOTES: 11. VDSS = 30V; ID = 190A; rDS(ON) = 3.3m 12. VDSS = 30V; ID = 110A; rDS(ON) = 2.6m 13. VDSS = 30V; ID = 100A; rDS(ON) = 3.2m 14. All Above listed rDS(ON) values are at VGS = 10V
22
FN9131.3 February 15, 2007
ISL6144
TABLE 2. INPUT VOLTAGE = 12V TO 24V ILoad_Max 75A MOSFET PART NUMBER IRF1503S SUM110N03-03P STB100NF03L-03 N 3 3 3
Just a reminder, this is not an operating scenario, but it is rather a fault scenario and should not occur frequently. As explained above, different power supplies have different noise spectrum and might need adjustment of the VTH(HS). The following procedure can be used for VTH(HS) selection: Choose a value of VTH(HS) such that the net HS comparator threshold voltage is positive to allow turn-off only when VIN is lower than COMP. Take into account the worst-case of the HS Comp offset (VOS(HS) = +25mV to -40mV). A good starting value is 55mV. The sum of R1 and R2 is not to exceed 50k. It is suggested to choose R2 = 47.5k and calculate R1 according to Equation 17:
V TH ( HS ) R 1 = ---------------------------------------------------------------- R 2 V REF ( VSET ) - V TH ( HS ) (EQ. 17)
NOTES: 11. VDSS = 30V; ID = 190A; rDS(ON) = 3.3m 12. VDSS = 30V; ID = 110A; rDS(ON) = 2.6m 13. VDSS = 30V; ID = 100A; rDS(ON) = 3.2m 14. All Above listed rDS(ON) values are at VGS = 10V
Another important consideration when choosing the ORing MOSFET is the forward voltage drop across the drainsource. If this drop approaches the 0.41V limit, (which is used in the VOUT fault monitoring mechanism), this will result in a permanent fault indication. Normally, this voltage drop is chosen to be less than 100mV.
R1 = 499 R1 resistor connected between VOUT and COMP pins R2 resistor connected between COMP and VSET pins VREF(VSET) = 5.3V 1. Operate all parallel feeds in current sharing mode (either by using current sharing techniques or by simply adjusting the voltages very close to each other for natural current sharing). 2. Vary the load current from 1A to its maximum value, monitor the gate voltages, and make sure all gates are on (note that at very light loads the current sharing scheme might stop functioning and only one feed carries this light current, at this point gate voltages will be just above the gate threshold, and even maybe one gate will be on while the others are not). 3. If at medium to maximum load currents all feeds have their gates on, then the chosen VTH(HS) is suitable. 4. If only one feed has its gate on, the threshold value is too low and the gate is turning off due to power supply noise and needs to be increased. Also, the feeds may not be sharing the load current due to discrepancy in output voltages and current sharing failure. 5. Verify the current sharing scheme and output voltages. If the output voltages and currents of each feed are equal but one or more of the gates is still off, increase VTH(HS) by increasing R1 in 250 to 500 increments (this increases VTH(HS) by 25mV to 50mV) until all feeds have their FETs turned on.
Setting the External HS Comparator Threshold Voltage
Typically, DC/DC modules used in redundant power systems have some form of active current sharing to realize the full benefit of this scheme including lower operating temperatures, lower system failure rate, as well as better transient response when load step is shared. Current sharing is realized using different techniques; all of these techniques will lead to similar modules operating under similar conditions in terms of switching frequency, duty cycle, output voltage and current. When paralleled modules are current sharing, their individual output ripple will be similar in amplitude and frequency and the common bus will have the same ripple as these individual modules and will not cause any of the turn-off mechanisms to be activated as the same ripple will be present on both sensing nodes (VIN and VOUT). This would allow setting the high speed comparator threshold (VTH(HS)) to a very low value. As a starting point, a VTH(HS) of 55mV could be used, the final value of this TH will be system dependant and has to be finalized in the system prototype stage. If the gate experiences false turn-off due to system noise, the VTH(HS) has to be increased. The reverse current peak can be estimated as:
V TH ( HS ) + V SD V OS ( HS ) I REVERSEP = ---------------------------------------------------------------------- ; where r DS ( ON ) (EQ. 16)
VSD is the MOSFET forward voltage drop
VOS(HS) is the voltage offset of HS Comparator
The duration of the reverse current pulse is in the order of a few hundred nanoseconds and is normally kept well below the current rating of the ORing MOSFET. Reducing the value of VTH(HS) results in lower reverse current amplitude and reduces transients on the common bus voltage. 23
FN9131.3 February 15, 2007
ISL6144
PRIME_PS START SET VTH(HS) = 55mV R1 = 499 R2 = 47.5k C5* GATE 5V R3 LED1 FAULT RED OPERATE ALL FEEDS IN CURRENT SHARING MODE (VIN1 = VIN2 =...= VINn) n = N+1 GND VIN C1 VOUT ISL6144 R1 HVREF COMP R2 VSET C2 VOUT Q1 C6*
BACKUP_PS C7* GATE 5V R4 LED2 FAULT VIN C3
Q2 C8* VOUT ISL6144 R6 HVREF COMP R7 VSET GND
C4
INCREASE
NO
VTH(HS) (BY INCREASING R1 ONLY)
COMPARE GATE-SOURCE VOLTAGES VGS1 VGS2 ...VGSn
RED
FIGURE 33. USING ISL6144 FOR BACKUP REDUNDANCY
YES
STOP
Remote Sense in Redundant Power Systems
Remote output voltage sensing is a feature implemented in most of today's power supplies. This feature is used to compensate for any resistive voltage drops between the power supply output and the load-connection point. The remote sensing pin (RS/+S) must be connected as close as possible to the load in order to compensate for any resistive voltage drops across the power path from the power supply output to the load. The output of many such power supplies can be connected in parallel to provide redundancy and fault tolerance. An ORing device (MOSFET/Diode) is typically used to provide the required isolation of any fault on the power supply side from propagating to the load side. In this case it is not recommended to connect the remote sense pins of the parallel units to the Common Bus point (at load terminals), as this can provide an alternative path for fault currents. The remote sense pins can be connected on the input side of the ORing device to compensate for any drop prior to it. Using an ORing MOSFET (compared to an ORing diode) reduces the forward voltage drop. By using a low rDS(ON) N-Channel ORing MOSFET in redundant power systems, the forward voltage drop can be reduced to less than 100mV. This is another advantage over the ORing diode solution (that has 400mV to 600mV drop) when tight regulation is imposed on the Common Bus voltage. If remote sense is absolutely required, one has to make sure that it will not lead to fault propagation when one power supply output is shorted. The remote sense configuration has to be looked at and design precautions has to be made to make sure the redundancy and fault tolerance are not compromised by the remote sense connection to the Common Bus.
USE CURRENT VALUES of R1 AND VTH(HS)
FIGURE 32. SELECTING VTH(HS) VALUE
Configuring ISL6144 for Backup Redundancy (Rail Selector)
The ISL6144 can be used as a rail selector in applications with backup redundancy. In this case, the backup power source voltage (for example battery) should be selected in such a manner that it is lower than the prime source voltage. Prime_PS > Backup_PS Also, the voltage difference between the two rails has to be higher than the High Speed Comparator threshold voltage. Prime_PS - Backup_PS >> VTH(HS)
24
FN9131.3 February 15, 2007
ISL6144 PCB Layout Considerations
The ISL6144EVAL1 uses a 4 layer PCB with 1oz external layers and 2oz internal layers, dedicated ground and power planes are used to insure good efficiency and EMC performance. Other layer stack-up and thickness is possible depending on the particular power system. The power traces are designed to handle at least 20A of load per feed. Power and ground planes are made of 2oz copper and external signal/power layers are 1oz copper. The loop area for all power traces is minimized to reduce parasitic inductance. A ground island can be created under the IC and connected to the power ground at a single point for reduction of noise that may be injected from the power ground into the IC ground. SOURCE1 - TP1, TP17 DRAIN1 - TP2, TP18 GATE1 - TP13 HVREF1 - TP9 COMP1 - TP11 VSET1 - TP10 FAULT1 - TP3 VIN2 - J7 SOURCE2 - TP4, TP21 DRAIN2 - TP5, TP22 GATE2 - TP14 HVREF2 - TP8 COMP2 -TP12 VSET2 - TP7 FAULT2 - TP6 VOUT - J2 and J5 (connect to J1 when VOUT replace LED AUX PS) GND - J3, J6, J8, TP24-TP27 V+5V - (AUX PS for LEDs) - J1
Component Selection Summary
Component selection is listed for one feed and is applicable for all other parallel feeds. R1, R2 - are resistors that define the HS comparator threshold voltage used in the high speed turn-off. The sum of R1+ R2 50k. R1 and R2 are found using Equation 17. R3 - is a pull-up resistor on the FAULT pin that can be used if LED1 is not used. FAULT is an open drain that can be used to interface with an optocoupler, LED or directly to a logic circuit. This resistor is not populated on the EVAL board. R4 - is the FAULT pin LED current limit resistor, R4 is chosen to have an LED current of about 4mA. C1 - is the HVREF Capacitor, placed between VIN and HVREF pins, this capacitor is necessary to stabilize the HVREF(VZ) supply and a value of 150nF is sufficient. Increasing this value will result in gate turn-on time increase. C2 - is the COMP Capacitor, Placed between VOUT and COMP pins to provide filtering and decoupling. A 10nF capacitor is adequate for most cases. C5, C6 - are VIN and VOUT local decoupling capacitors, help immunize the pins against transients that might result in case of fast speed gate turn-off. Q1-Q3 - are ORing MOSFET(s), number of paralleled MOSFETs depends on device rDS(ON), maximum allowable losses and junction temperature of the ORing MOSFETs. U3 - is Intersil's ISL6144 High Voltage ORing MOSFET Controller IC. LED1 - is a red LED used to indicate first feed faults. When VIN1 is off while VOUT and auxiliary 5V supply are present LED1 will be red. List of Test Points and Connectors VIN1 - J4
25
FN9131.3 February 15, 2007
ISL6144 ISL6144EVAL1 Schematics
J1 EXTERNAL 5V VAUX1 V + 5V VIN1 J4 VIN1 FROM PS1 TP17 TP1 U3 2 C1 150nF 10V TP9 VIN 1 FDB3632 Q1 GATE1 Q2 SOURCE1 DNP
Q3
DNP
DRAIN1
TP18
TP2 TP13 GATE VOUT 15 R1 499 C2 10nF 10V R3 4.99k DNP VAUX1 R3 1.21k 1 2 LED1
2 3 J6
TP28 VIN1 4
3 4 5
HVREF NC1
COMP ISL6144
1
C5 100nF 100V
NC2 6 NC3 TP24 7 NC4 8 GND
14 VSET NC8 13 NC7 12 11 NC6 NC5 10 9
R2 TP11 47.5k TP10 C7 100nF 100V TP3
FAULT
FAULT INDICATION LED AND PULL UP Q6 DNP TP25 TP28 3 Q5 DNP VIN2 J7 VIN2 FROM PS2 TP29 VIN2 4 2 C3 150nF 10V C6 100nF 100V SOURCE2 FDB3832 Q4 2 1
VOUT TP15 4 VOUT GND
DRAIN2
TP22
TP21 1
TP4 TP5 GATE2 U4 VIN TP14 GATE VOUT 16 15 R6 499 C4 10nF 10V VAUX1 R9 1.21k 1 2 LED2 1
2 3 J8
3 HVREF 4 NC1 5 NC2 6 NC3
COMP ISL6144
VOUT J5
TP8
TP27 7 NC4 8 GND
R7 TP12 47.5k C8 VSET 14 13 100nF TP7 100V NC7 12 11 NC6 TP6 NC5 10 9
R8 4.99k DNP
FAULT
26
FN9131.3 February 15, 2007
ISL6144 Bill of Material
TABLE 3. BILL OF MATERIALS COMPONENT CONTROL BOARD BOM R1, R6 R2, R7 R3, R8 R4, R9 LED1 LED2 C1, C3 C2, C4 C5, C6 C7, C8 Q1-Q3 Q4-Q6 U3, U4 U5, U6 VTH(HS) Programming Resistor VTH(HS) Programming Resistor FAULT Pull-up Resistor FAULT LED Current Limit Resistor Feed 1 Fault Indication RED LED Feed 2 Fault Indication RED LED HVREF Capacitor COMP Decoupling Capacitor 499, RNC55, 1/8W 47.5k, 0603, 1/8W 4.99k, 0603, 1/8W 1.21k, 0603, 1/8W Red LED, 0805 ceramic Red LED, 0805 ceramic 150nF, SM1206, 10V 10nF, SM0805, 10V 100nF, SM1206, 100V 100nF, SM1206, 100V FDB3632, 100V, 9m, D2PAK FDB3632, 100V, 9m, D2PAK ISL6144IV, 10V to 75V ISL6144IR, 10V to 75V TH on EVAL board, could be replaced by SMT SMT, 0603 SMT, 0603 (DNP) SMT, 0603 (used with LED connected to +5V) SMT SMT SMT SMT SMT SMT Q2, Q3 - DNP (populate for higher current applications if needed) Q5, Q6 - DNP (populate for higher current applications if needed) TSSOP16 20 Ld QFN 5X5 - DNP (alternative footprint) NAME SIZE, VALUE, RATING DESCRIPTION/COMMENTS
VIN Pin Decoupling Capacitor
VOUT Pin Decoupling Capacitor Feed 1 ORing MOSFET(s) Feed 2 ORing MOSFET(s) ORing MOSFET Controller ORing MOSFET Controller
NOTE: DNP = Do Not Populate
27
FN9131.3 February 15, 2007
ISL6144 Thin Shrink Small Outline Plastic Packages (TSSOP)
N INDEX AREA E E1 -B1 2 3 L 0.05(0.002) -AD -CSEATING PLANE A 0.25 0.010 GAUGE PLANE 0.25(0.010) M BM
M16.173
16 LEAD THIN SHRINK SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A A1 A2 b c D MIN 0.002 0.033 0.0075 0.0035 0.193 0.169 0.246 0.020 16 0o 8o 0o MAX 0.043 0.006 0.037 0.012 0.008 0.201 0.177 0.256 0.028 MILLIMETERS MIN 0.05 0.85 0.19 0.09 4.90 4.30 6.25 0.50 16 8o MAX 1.10 0.15 0.95 0.30 0.20 5.10 4.50 6.50 0.70 NOTES 9 3 4 6 7 Rev. 1 2/02
A1 0.10(0.004) A2 c
E1 e E L N
e
b 0.10(0.004) M C AM BS
0.026 BSC
0.65 BSC
NOTES: 1. These package dimensions are within allowable dimensions of JEDEC MO-153-AB, Issue E. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E1" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.15mm (0.006 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. Dimension "b" does not include dambar protrusion. Allowable dambar protrusion shall be 0.08mm (0.003 inch) total in excess of "b" dimension at maximum material condition. Minimum space between protrusion and adjacent lead is 0.07mm (0.0027 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact. (Angles in degrees)
28
FN9131.3 February 15, 2007
ISL6144 Quad Flat No-Lead Plastic Package (QFN) Micro Lead Frame Plastic Package (MLFP)
L20.5x5
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE MILLIMETERS SYMBOL A A1 A2 A3 b D D1 D2 E E1 E2 e k L N Nd Ne P 0.20 0.35 2.95 2.95 0.23 MIN 0.80 NOMINAL 0.90 0.02 0.65 0.20 REF 0.30 5.00 BSC 4.75 BSC 3.10 5.00 BSC 4.75 BSC 3.10 0.65 BSC 0.60 20 5 5 0.60 12 0.75 3.25 3.25 0.38 MAX 1.00 0.05 1.00 NOTES 9 9 5, 8 9 7, 8 9 7, 8 8 2 3 3 9 9 Rev. 4 11/04 NOTES: 1. Dimensioning and tolerancing conform to ASME Y14.5-1994. 2. N is the number of terminals. 3. Nd and Ne refer to the number of terminals on each D and E. 4. All dimensions are in millimeters. Angles are in degrees. 5. Dimension b applies to the metallized terminal and is measured between 0.15mm and 0.30mm from the terminal tip. 6. The configuration of the pin #1 identifier is optional, but must be located within the zone indicated. The pin #1 identifier may be either a mold or mark feature. 7. Dimensions D2 and E2 are for the exposed pads which provide improved electrical and thermal performance. 8. Nominal dimensions are provided to assist with PCB Land Pattern Design efforts, see Intersil Technical Brief TB389. 9. Features and dimensions A2, A3, D1, E1, P & are present when Anvil singulation method is used and not present for saw singulation. 10. Compliant to JEDEC MO-220VHHC Issue I except for the "b" dimension.
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 29
FN9131.3 February 15, 2007

▲Up To Search▲

Price & Availability of ISL614407

	To Download ISL614407 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .